VHDL code for Serial-In Parallel-Out (SIPO) shift register

SIPO is the process of loading the data serially one bit at a time in the register, output of stored data is available in the parallel form.

VHDL code:

library ieee; 

use ieee.std_logic_1164.all; 

entity sipo is 

port(clk,si: in std_logic; po : inout std_logic_vector(7 downto 0) ); 

end sipo; 

architecture arch of sipo is 

begin 

process(clk) 

begin 

if (clk='1' and clk'event)then 

po(7 downto 1) <= po(6 downto 0); po(0) <= si; 

end if; 

end process; 

end arch;